An interrupt or an exception signals a processor that some special internal or external condition requires attention. Upon receiving such a signal, a processor suspends the current process and starts executing a routine to handle the special condition. This routine is referred to as a handler. The handler's task typically consists of determining the source and cause of the special condition, handling of the condition, and resuming the suspended process (if the process has not been terminated).
To help the software identify the cause of an interrupt or exception quickly, each special condition may be assigned a distinct number called a vector or vector number. This assignment is part of a given processor instruction set architecture (ISA). For example, the ISA of the Intel® Pentium® 4 (referred to herein as the IA-32 ISA) assigns a vector number to each exception (e.g., vector 0 corresponds to a divide error and vector 14 corresponds to a page fault), but leaves open the vector assignment of interrupts (e.g., interrupts generated by the network interface hardware).
To speed up interrupt and exception processing, an architecture may define a structure, called the interrupt descriptor table (IDT), which holds an entry per vector. Each entry contains a descriptor (e.g., an interrupt gate, trap gate or task gate in the IA-32 ISA) specifying the location of the corresponding handler. This design allows software to install distinct handlers for each interrupt or exception that has been assigned a vector. Some ISAs may utilize a single vector for all exceptions and/or interrupts.
When the processor detects a special condition, it fetches the IDT entry corresponding to the current condition and determines the pointer to the beginning of the associated handler. In ISAs utilizing a single vector for all exceptions and/or interrupts, no indexing of an IDT is required; the pointer to the beginning of the associated handler is determined from the single vector. The processor next saves the state of the process currently running (e.g., its instruction pointer), and jumps to the beginning of the handler using the extracted pointer. This process is referred to as delivering a fault.
In some ISAs, for some kinds of exceptions, an error code may be pushed onto the stack prior to jumping to the beginning of the handler. Alternatively, an eror code may be provided in a hardware register, one or more memory locations, or using some other means. The error code provides to the handler additional information regarding the exceptional condition (e.g., an identifier for a faulting segment register).
In some ISAs, exceptions may occur while delivering interrupts or exceptions. For example, in the IA-32 ISA, the processor may encounter a number of exceptions during delivery of the interrupt or exception to the handler, such as a page fault resulting from the page where the IDT resides being marked not present in the page tables. In this case, the processor delivers a page-fault exception instead of the interrupt.